The correction of random bit errors is a key requirement for digital transmission systems. A number of techniques, for example parity checking and the use of coded sequences have been described for performing this function. A general discussion of error correction techniques is given "Error Control Coding" by Shu Lin and David J. Costello Jnr (Prentice Hall-ISBN 0-13-283796-X). Reference is also directed to specification No. U.S. Pat. No. 5,367,544 which describes a modified CRC decoder which uses parity check bits for frame synchronisation as well as for the usual detection and possible correction of the header.
In particular, error correction is becoming increasingly important in ATM (asynchronous transfer mode) and other digital transmission systems where traffic from a number of different users is multiplexed together into ATM cells or into virtual containers which are routed over a common connection. A particular problem with these systems is that of error multiplication where payloads have been scrambled and subsequently descrambled. This can lead to duplication of errors within a cell, or, depending on the position of the error in a cell, the introduction of a duplicated error in the next cell. Present systems do not differentiate between these duplicated errors and isolated errors and this can lead to miscorrection of some errors and thus to the introduction of new errors.